Conventional dynamic random access memory (DRAM) may include a large number of memory cells and control circuits. The memory cells may form an array of memory cells with each memory cell including a switch and a capacitor. The memory cells may be arranged in rows and columns in the array of memory cells. The switch may provide access to the capacitor, which stores charge representing a high or low logic state. The charge stored in a memory cell may represent a bit of data, which may be combined with other bits to produce bytes or words of data. The control circuits may be configured to allow data to be read from or written to the array of memory cells responsive to received memory commands.
Due to process variations and impurities, defects may occur during the DRAM fabrication process. The defects may result in one or more memory cells being defective. The defective memory cells may not operate as intended, which may result in bad memory cells within the array of memory cells. The defective memory cells may be uncovered during testing DRAM die undergo during and after fabrication. Redundant memory cells, e.g., columns and/or rows of redundant memory cells, may be included in the DRAM so that defective cells may be replaced. For example, a full column or row of cells may that contain one or more defective cells may be replaced by a redundant column or row of cells. In order to replace a row or column that contains a defective memory cell, a physical address of the row/column that includes the defective cell may need to be stored by the DRAM in a non-volatile manner. The address of the replacement row/column may also need to be stored. The control circuits may access the stored physical address when writing and/or reading operations are performed so that the replacement row/column is accessed instead of the row/column that includes the defective memory cell.
Due to the perpetuity of the defective memory cells and the corresponding replacement rows/columns, the physical address of their locations may need to be permanently stored. Yet, the memory cells of a DRAM are volatile, and charge stored in a DRAM memory cell may last only a short time. As such, storing physical addresses of the defective and/or replacement rows/columns in a standard DRAM memory cell may not be as permanent as desired. While prior solutions may have included non-volatile memory cells fabricated with DRAM memory cells, or even using DRAM cells as non-volatile cells, these solutions have drawbacks. For example, fabricating non-volatile and volatile cells on a same die may produce fabrication difficulties and require different control circuits, which may lead to excessive die area. The prior attempts at using DRAM memory cells as non-volatile cells may have also been die area intensive.